1. Field of the Invention
The present invention relates to a semiconductor memory apparatus having a first cell group of memory cells of a specified row in a memory cell array, a second cell group of memory cells of either a row immediately before the specified row or a row immediately after the specified row and a common source line disposed therebetween. More particularly, the present invention relates to a semiconductor memory apparatus in which even when the effective channel length of the memory cells on one side of the common source and that on the other side of the common source are different from one another, a large determination margin can be provided for the memory cells on both sides.
2. Description of the Prior Art
For example, U.S. Pat. No. 5,386,158 describes a conventionally known technique that uses comparison cells for determining whether a value stored in a flash EEPROM (hereinafter flash memory) is "0" or "1". This technique, which is the background technique, will be described with reference to FIG. 9.
As shown in FIG. 9, a memory cell array 1 is formed from split gate type memory cells. In the memory cell array 1, a first cell group of memory cells (only memory cells 11 and 13 shown in this example) of a specified row (an odd-number row R.sub.2m-1 in this example) and a second cell group of memory cells (only memory cells 12 and 14 shown in the example) of a row immediately before or a row immediately after the specified row (an even-numbered row R.sub.2m to in this example) are disposed to form a pair for the two rows. Source regions S1-S4 of the respective memory cells are connected to a common memory cell source line 3. Each two of the memory cells (in this example, 11 and 12, and 13 and 14) for each column (column C.sub.n or C.sub.n+1 in this example) form a memory cell pair in which the source line 3 is disposed (symmetrically, in this example) therebetween. In FIG. 9, m=1, 2, . . . , M/2 (where M is the number of rows), and n=1, 2, . . . , N (where N is the number of columns of the memory cell array).
A word line WL.sub.2m-1 is connected to control gates CG1 and CG3 of the respective memory cells 11 and 13 of the row R.sub.2m-1, and a word line WL.sub.2m is connected to control gates CG2 and CG4 of the respective memory cells 12 and 14 of the row R.sub.2m. A Bit line BL.sub.n is connected to drain regions D1 and D2 of the respective memory cells 11 and 12 that belong to the column C.sub.n, and a Bit line BL.sub.n+1 is connected to drain regions D3 and D4 of the respective memory cells 13 and 14 that belong to the column C.sub.n+1.
In FIG. 9, a read circuit 7 includes a comparator unit 71, a comparison cell 72, and sense amplifiers 731 and 732. A source region S of the comparison cell 72 is connected to a comparison cell source line 81. Although not shown, the source line 81 and the source line 3 of the memory cell array 1 described above have the same potential, and the comparison cell 72 and the memory cells 11 and 13 are oriented in the same direction.
A comparison signal REF (drain current Id.sub.r) from the comparison cell 72 is inputted in the sense amplifier 731. A read signal WS (drain current Id.sub.w) from the memory cell is inputted in the sense amplifier 732. The amplification factor of the sense amplifier 732 is set to be smaller than the amplification factor of the sense amplifier 731. The comparator unit 71 compares an output REF' (drain current Id.sub.r ') of the sense amplifier 731 and an output WS' (drain current Id.sub.w ') of the sense amplifier 732 to thereby determine as to whether a stored value of the memory cell to be read out is "0" or "1" (in other words, in a written state or an erased state).
In FIG. 9, when physical addresses A.sub.0, A.sub.1, . . . A.sub.k, of the memory cell array 1 are designated, a row address decoder 41 decodes lower bits A.sub.0, A.sub.1, . . . A.sub.j, a column address decoder 42 decodes upper bits A.sub.j+1, A.sub.j+2, . . . A.sub.k, a multiplexer 43 transmits a read signal WS (drain current Id.sub.w) coming from the memory cell to the sense amplifier 732 based on a signal from the column address decoder 42.
It is noted that the memory cells forming the memory cell array 1 and the comparison cell 72 provided in the read circuit 7 include components that are normally, simultaneously formed on the same substrate with the same manufacturing process. As a result, for example, a mask alignment for forming floating gates 111 and 121 may deviate from a mask alignment for forming control gates 112 and 122 for the respective memory cells 11 and 12 (in FIG. 10, designed locations of the floating gates are indicated by .alpha.1 and .alpha.2, respectively).
A common source region 103 and drain regions 114 and 124 of the respective memory cells 11 and 12 are formed after the floating gates 111 and 121 and the control gates 112 and 122 are formed. In other words, dopants for forming the source region and the drain regions are implanted from above the floating gates and the control gates. As a result, if a mask alignment error, such as the one described above, occurs, the effective channel length of the memory cell 11 and that of the memory cell 12 may be different from one another. For example, when the effective channel length L1 of the memory cell 11 is longer than the original channel length L0 by .delta., the effective channel length L2 of the memory cell 12 is shorter than the original channel length L0 by .delta.. In other words, L1=L0+.delta., and L2=L0-.delta.. Therefore, the difference in the effective channel length between the memory cells 11 and 12 is 2 .delta..
On the other hand, although not shown in FIG. 10, the comparison cell 72 shown in FIG. 9 is normally formed to be oriented in the same direction of one of the memory cells 11 and 12. As a result, the effective channel length of the comparison cell 72 is different from the effective channel length of one of the memory cells 11 and 12. For example, if the comparison cell 72 and the memory cell 11 are oriented in the same direction, the effective channel length of the memory cell 11 and the comparison cell 72 is defined by L1=L0+.delta.. Therefore, the effective channel length of the memory cell 12 is defined by L2=L0-.delta.. Accordingly, the difference in the effective channel length between the memory cell 11 or the comparison cell 72 and the memory cell 12 is 2 .delta..
As a result, although the memory cell 11 and the comparison cell 72 have the same Vcg/Id (Vcg: control gate voltage, and Id: drain current) characteristic, those of the memory cell 12 and the comparison cell 72 are substantially different from each other. This tendency becomes substantially noticeable in the erased state (in which electrons are not stored in the floating gate) (which will be described later with reference to FIG. 4B and FIG. 5B).
For example, FIGS. 11A and 11B are graphs illustrating drain currents Id in memory cells in odd-numbered rows and even-numbered rows when the memory cells in the erased state and in the written state (in which electrons are stored in the floating gate) are read. FIG. 11A shows drain currents in the erased state, and FIG. 11B shows drain currents in the written state. As shown in FIGS. 11A and 11B, the drain currents Id in the odd-numbered rows and in the even-numbered rows are different in magnitude regardless of whether the memory cells to be read are in the erased state or in the written state, and the differences become particularly noticeable in the erased state.
Also, if a mask alignment error such as the one shown in FIG. 10 occurs, the capacity ratio of the memory cell 11 (and also that of the comparison cell) differs from the capacity ratio of the memory cell 12. The term "capacity ratio" is defined by a ratio of the capacity between the control gate and the floating gate and the capacity between the floating gate and the source region. The capacity ratio determines a potential of the floating gate when the control gate is charged with a potential. Therefore, when the capacity ratios are different, the characteristics such as threshold values of the memory cells differ from one another.
Therefore, when the characteristics of the memory cells substantially differ from one another, the number of defective memory cells in which reading cannot be normally performed increases, or there is a greater possibility that defective flash memories are manufactured, lowering the manufacturing yield. As a consequence, a greater accuracy in the mask alignment is required in the manufacturing process. Also, determination margins in determining read signal values substantially vary from one another. As a consequence, for example, when the service life of products is considered based on deterioration of the endurance of flash-memories, product catalogs must recite the service life of a flash memory that has the largest effective channel length difference 2 .delta.. As a result, the service life of those flash-memories that are still usable is immaturely terminated substantially earlier than it should be. Therefore, for example, even when a flash memory is still usable, the user determines, by referring to the number of accesses, that the flash memory has reached the product life, and may unnecessarily replace the flash memory.
Also, since there are great variations in the determination margins, there is a certain limitation to implementing multiple memory level values (for example, increasing the memory level from two values to four values, eight values, and the like) in each memory cell. In addition, in the conventional flash-memories, the effective channel length difference 2 .delta. does not change regardless of the size of the memory cells. Therefore, the smaller the size of memory cells (in other words, the smaller the designed value of the channel length), the greater the ratio between the longer effective channel length (L0+.delta.) and the shorter effective channel length (L0-.delta.). This prevents higher integration of flash memories.